1. Field of the Invention
The invention relates generally to channel stress within field effect devices. More particularly, the invention relates to efficient methods for inducing channel stress within field effect devices.
2. Description of the Related Art
Field effect devices, such as but not limited to field effect transistor devices, are common semiconductor devices that are used within semiconductor circuits. In particular, field effect transistor devices have been effectively scaled in dimension over the period of several decades to provide semiconductor circuits with increasing levels of integration and increasing levels of functionality.
Recent advances in performance of field effect devices have focused upon both a selection of a particular crystallographic orientation of a semiconductor substrate upon which is fabricated a field effect device, as well as introduction of a particular channel stress within the particular crystallographic orientation of the semiconductor substrate within which is fabricated the field effect device. In that regard, for example, electron mobility within an nFET device is typically enhanced by a compressive stress within a vertical direction within a 100 crystallographic orientation silicon or silicon-germanium alloy semiconductor substrate upon which is fabricated the nFET device. In comparison, and also for example, a hole mobility within a pFET device is typically enhanced by a tensile stress within a vertical direction within a 110 silicon or silicon-germanium alloy semiconductor substrate upon which is fabricated the pFET device.
While mechanical stress effects are thus desirable to provide enhanced performance within field effect devices within semiconductor substrates, mechanical stress effects within field effect devices within semiconductor substrates are nonetheless not entirely without problems. In that regard, mechanical stress effects are often difficult to reliably and uniformly reproduce as field effect device dimensions, including channel length dimensions and device pitch dimensions, decrease.
Various crystallographic effects and related mechanical stress effects with respect to semiconductor devices and semiconductor structures are known in the semiconductor fabrication art.
For example, Kasukabe, et al., in “Epitaxial growth of (001)-oriented titanium nitride thin films by N implantation,” J. Vac. Sci. Technology A, 16(2), March/April 1998, teaches that lattice strain effects influence crystallographic orientation transitions when fabricating a titanium nitride layer incident to nitrogen ion implantation of a titanium layer located upon a monocrystalline substrate.
Semiconductor substrate crystallographic effects, and related mechanical stress effects, are likely to be of continued prominence as semiconductor technology advances. To that end, desirable are semiconductor structures and methods for fabrication thereof that provide for efficient introduction of desirable channel stress within particular crystallographically oriented semiconductor substrate channels within semiconductor devices.